RHCPP 01-34 (CONF)
2001

 
 

Royal Holloway Centre for Particle Physics


High Level Triggers in ATLAS - Design and Performance
Atlas PESA Group (S George et al)
Abstract

The trigger and data-acquisition system of ATLAS, a general-purpose experiment at the Large Hadron Collider (LHC) will be based on three levels of online selection. Starting from the bunch-crossing rate of 40 MHz (an interaction rate of 1 GHz at design luminosity - 1034 cm-2s-1), the first level trigger (LVL1) will reduce the rate to about 75 kHz, using purpose-built hardware. An additional factor of about 103 in rate reduction is to be provided by the High-Level Triggers (HLT) system, with its two main functional components: the second level trigger (LVL2) and the Event Filter (EF).

The HLT hardware architecture is going to use mostly commodity components (e.g. for processors and for network elements), allowing the algorithms to be implemented in a high level language and ensuring a flexible boundary across the two selection levels. LVL2 has to provide a fast decision (guided by the information from LVL1), using only a fraction of the full event, however already at full granularity, and can combine all sub-detectors. At the EF, a refined selection is done, with the capability of full event reconstruction and the use of detailed calibration and alignment parameters.

The HLT software architecture will provide a common and rather "lightweight" framework, able to execute the various selection algorithms and to control the sequence of execution according to the event properties and configuration parameters. The system will be very flexible to adapt to changes e.g. in luminosity and background conditions.

This paper will present the approach chosen for the software design of the HLT selection framework and of the algorithm interface, giving examples for selection sequences and algorithms. Based on currently existing prototypes, results for both the expected physics (signal efficiency, background rejection) and system (execution time, data bandwidth) performance will also be shown.

 
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Also published in:
12th IEEE-NPSS Real Time Conference Proceedings 2001